This invention relates generally to monolithic microwave integrated circuits and more particularly to field effect transistors.
As is known in the art, monolithic microwave integrated circuits (MMIC) are used in radio frequency systems such as radars and the like. One type of MMIC circuit is an r.f. phase shifter using field effect transistors as the switching elements to switch a capacitance into or out of a circuit. Examples of such phase shifters are described in an Article entitled Monolithic 6-18 GHz 3Bit Phase Shifter by Schindler et al., 1985 IEEE GaAs IC Symposium Digest, pp. 129-132.
As is known, a field effect transistor includes a gate or control electrode, source and drain electrodes. In the above-mentioned reference, the field effect transistor is operated in a passive mode having the gate electrode fed by a D.C. bias which is used to control the conductivity between the drain and source electrodes. Capacitors or inductors are generally connected between the drain and source electrodes of the FET to provide switchable phase shift elements. The gate bias voltage is used to switch the drain and source channel region between an "on state" or low impedance state and "pinch-off" or high impedance state of the transistor. When the transistors are switched into the pinch-off state, the capacitors and inductors are switched into the circuit.
The actual impedance characteristic between source and drain electrodes in the "on" state of the transistor is a low impedance resistance (i.e. the channel resistance) in series with a parasitic inductance. Whereas the actual impedance characteristic in the pinch-off state of a transistor having a capacitor across source-drain electrodes is the capacitance of the switched capacitor in series with relatively high parasitic inductances. The conventional layout for a capacitor connected across source and drain electrodes requires the use of relatively long source and drain interconnect lines to the capacitor. These source and drain interconnects present the high parasitic inductance in series with the capacitance, as mentioned above. These high value inductances are undesirable when the transistor is employed as a switchable element in a phase shifter, since it leads to phase shift errors, and also reduces the bandwidth of the phase shifter.
It is also known that field effect transistors operate with gate and drain biases to provide amplification. One common amplification scheme is a distributed amplifier. As known, a distributed amplifier uses a plurality of field effect transistors having gate electrodes successively coupled by gate or input transmission line and drain electrodes successively coupled by a drain or output transmission line. It is generally desirable in distributed amplifiers to have equal impedance (Z) and phase velocities (VP) for the drain and gate lines. The impedance Z is given by Z= L/C, and the phase velocity is given by VP = L.multidot.C where L is the per unit distributed inductance and C is the inherent input or output capacitance of the transistors.
In general, the input capacitance C.sub.GS is much larger than the corresponding drain to source capacitance C.sub.DS. One way to achieve equal phase velocity and equal impedance between gate and drain lines is to modify the inherent capacitance either by increasing the drain to source capacitance or reducing the gate to source capacitance. A scheme for reducing gate to source capacitance is shown in U.S. Pat. No. 4,543,535 assigned to the assignee of the present invention. This technique, however, is not desirable if high output power is not required, since it requires the use of a larger field effect transistor which makes the circuit larger. Therefore, it is often necessary to increase the drain to source capacitance. This is generally accomplished indirectly by using a series drain inductance which makes the effective drain to source capacitance appear large at the end of the drain line. The required series drain inductance can be quite large in order to provide an effectively large capacitance. A large inductance thus also provides for a large circuit. Therefore, it would be desirable to provide a capacitor across drain/source electrodes of the field effect transistor to provide an effectively larger capacitance. This capacitor would be physically smaller than the required inductance thus reducing the circuit size.
The problem with this approach, however, is that the effective capacitance required is quite small. With a small value capacitance, the parasitic inductance associated with adding the capacitor can dominant the overall reactance characteristic. This characteristic must be capacitive, however, for proper operations of such transistors as part of a distributed amplifier.
A conventional transistor 10 having an external capacitor 25 is shown in FIGS. 1, 1A to include spaced parallel gate electrodes 14a-14d coupled to a common gate electrode pad 14 which is disposed off of a semiconductor active region 13. The semiconductor active region 13 is here an epitaxially grown active region and includes a moderately doped semiconductor layer 13a and a more highly doped, high conductivity contact layer portions 13b as is generally known. Drain electrodes 16a-16c and source electrodes 18a-18b have contact portions 16a'-16c' and 18a', 18b'disposed over regions 13b. The gate electrodes 14a-14d space the source and drain electrodes. The drain contacts 16a1.varies.16c are coupled to a common drain pad 16 disposed off of the mesa shaped semiconductor region 13a, and the source contacts 18a-18b are coupled to a common, off mesa source electrode 18 via airbridges 19a and 19b. A capacitor 25 is disposed off of the mesa active region 13a and includes a bottom metalization layer 23 disposed over substrate 12 and connected to the drain metalization 16c. The bottom metalization 23 provides one of the plates of the capacitor. Since a passivation layer 22 is commonly disposed over such transistors, the passivation layer 22 is extended over the bottom metalization layer 23 and forms a dielectric layer for the capacitor 25. A top metalization 24 is also disposed over the passivation layer 22 and provides an upper plate for the capacitor 25. The top layer of metalization 24 is connected to the common source electrode 18 by an airbridge 19c, as shown FIG. 1).
Several problems are provided by this particular arrangement. For example, the arrangement imposes a number of parasitic inductances into the transistor structure making modeling of the field effect transistor and the capacitor relatively difficult. These parasitics also degrade actual performance. The parasitics are principally the result of the relatively long electrical connections between source and drain electrodes and the capacitor. These lengths are represented by arrows l.sub.1 and l.sub.2 respectively. Moreover, since the capacitor is disposed off of the mesa portion of the FET, the presence of the capacitor increases the size of the transistor which is also generally undesirable since this also increases the magnitude of parasitic reactances referred to above. Moreover, the FET and shunt mounted capacitor also occupy more physical space which increases cost of the transistor and can also reduce circuit yields.